Field of the Invention
The present invention relates to a solid-state image sensor and an electronic device including the same.
Description of the Related Art
There has recently been devised a device such as an image sensor in which an analog signal processing unit and a digital signal processing unit including a logic, a memory, and the like are embedded in one chip. For example, an analog signal processing unit and a digital signal processing unit are formed in different semiconductor layers and stacked in the wafer level or chip level, thereby forming a one-chip device without loss of integration in each layer.
FIG. 13 is a block diagram showing the main part of a conventional image sensor 80 such as a CMOS image sensor. Drive control to acquire a pixel signal is performed by a drive timing generation unit 81. Upon receiving a drive signal from the drive timing generation unit 81, charges are photoelectrically converted in a pixel array 82 and acquired as a potential. The voltage signal obtained from the pixel array 82 is digitized by an A/D conversion unit 84. The A/D conversion unit 84 is controlled by an A/D conversion unit control unit 83.
FIG. 14 is a block diagram showing the main part of an image sensor having a stacked structure and illustrating assignment to each semiconductor layer in a case where the analog signal processing unit and the digital signal processing unit of the image sensor shown in FIG. 13 are stacked. Referring to FIG. 14, a first semiconductor layer 90 is a layer including an analog signal processing unit, and a second semiconductor layer 96 is a layer including a digital signal processing unit.
Blocks 91, 92, 93, and 94 shown in FIG. 14 are equivalent to the blocks 81, 82, 83, and 84 shown in FIG. 13, respectively. In this example, however, the A/D conversion unit 94 and the control unit 93 are mounted on the side of the second semiconductor layer 96. In addition, a logic and a memory implemented as digital elements on the side of the second semiconductor layer 96 are implemented in a block 95 shown in FIG. 14.
The first semiconductor layer 90 and the second semiconductor layer 96 shown in FIG. 14 are stacked, as described above. When the semiconductor layers come close to each other, an electromagnetic wave or heat generated by the operations of the layers has an influence. To solve this problem, in Japanese Patent Laid-Open No. 2012-94720, a metal layer is formed in a region except a region where a through electrode is formed between stacked layers, and a function as a shield layer is imparted.
To connect signals of different semiconductor layers, a stable common potential (ground: to be referred to as GND hereinafter) needs to be set. However, the impedance between GNDs cannot be neglected in local GND connection. For this reason, a potential is formed between the GNDs of the layers and dynamically fluctuates in every operation wherein a current flows.
When a synchronization circuit design that operates based on a specific clock is employed on the digital layer side, the state of a status holding element (flip-flop circuit: to be referred to as an FF element hereinafter) is switched in synchronism with each edge (leading/trailing) of the clock. Hence, an enormous number of FF elements simultaneously consume the current. A current to be consumed by a combination logic (a combination circuit formed from an AND element/OR element and the like) connected to the output of the FF element also flows at the same timing.
The current consumption at the same timing on the digital layer side raises the potential of the digital-side GND and affects as an apparent power supply fluctuation. As a result, when A/D-converting a signal potential from the above-described stacked analog signal processing unit and acquiring a digital signal, the acquired potential of the analog signal or a reference potential used by the A/D converter fluctuates. This finally leads to periodic noise caused by digital signal processing and degrades image quality.